The UALink Consortium recently unveiled version 2.0 of its interconnect standard, designed to provide an open ecosystem alternative to Nvidia’s proprietary NVLink and NVSwitch technologies for large-scale AI compute clusters. While the organization is pushing to challenge Nvidia’s market dominance through rapid technical iteration, the first silicon based on the 1.0 standard is still months away from laboratory testing.
Currently, Nvidia dominates the AI infrastructure market through its proprietary high-speed interconnect technology. While this high-performance approach excels at managing massive GPU clusters, its high cost and exclusivity toward non-Nvidia hardware have driven the industry to seek more compatible, open-source alternatives. The UALink Consortium aims to build an Ethernet-like open standard that allows accelerators from different manufacturers to work together seamlessly.
Modular Architecture Boosts Development Efficiency
UALink Consortium Chairman Kurtis Bowman told the media that the 2.0 version introduces a new 200G Data Link and Physical Layer (DL/PL) specification. By decoupling the protocol layer from the I/O physical layer, the specification allows consortium members to develop for current 200G networks and future 400G networks independently, significantly shortening the technology iteration cycle.
Beyond physical layer upgrades, the 2.0 general specification adds support for "in-network compute." This technology reduces the volume of scheduling messages transmitted between GPUs, freeing up more bandwidth for core data streams and directly improving the execution efficiency of AI workloads. Additionally, the new Manageability Specification 1.0 ensures that UALink networks are compatible with mainstream data center management tools such as gRPC, YANG, and Redfish.
The consortium also plans to introduce chipset specifications that support embedding UALink technology directly into Systems-on-Chip (SoCs). This move will further lower deployment barriers, allowing a wider variety of devices to join the interconnect ecosystem without the need for standalone external chips.
Despite the finalized specifications, commercialization will take time. Bowman noted that silicon based on the 1.0 standard is expected to reach labs in the second half of 2026, with commercial products not hitting the market until 2027 at the earliest. For AI infrastructure providers eager to build "neocloud" architectures and break free from single-vendor dependency, the development of the UALink ecosystem remains a long-distance race.
